1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device provided with a contact plug layer connected to a semiconductor substrate and a pad electrode.
2. Background Art
In a manufacturing process of a semiconductor device, a barrier metal film for prevention of diffusion is provided at a portion at which different conductive materials are brought into contact with one another, such as a connecting portion between a semiconductor substrate and a contact layer.
A method of manufacturing a conventional semiconductor device provided with a barrier metal film will be described with reference to FIGS. 7A to 7C. FIGS. 7A to 7C show a method of forming a contact plug connected to a source/drain diffusion layer of a MOS transistor, for example. A description of a process for forming a gate oxide film and a gate electrode on an active region will be omitted herein for simplicity. As shown in FIG. 7A, element isolation regions 102 are first formed on a silicon semiconductor substrate 101 by the so-called shallow trench isolation method. Next, a conductive layer 103 composed an impurity of conductivity type opposite to the silicon semiconductor substrate 101 is formed on the silicon semiconductor substrate 101. A normally-used cobalt silicide film 104 is formed on the conductive layer 103 as a contact layer. The conductive layer 103 serves as a source/drain diffusion layer. Thereafter, an interlayer insulating film 105 is formed over the whole surface of the silicon semiconductor substrate 101 by a CVD method.
Next, as shown in FIG. 7B, the interlayer insulating film 105 is selectively etched to form a contact hole 106.
Next, as shown in FIG. 7C, deposition based on an inorganic CVD method using titanium tetrachloride (TiCl4) is done under the condition of temperatures ranging from about 400° C. to about 600° C. to form a titanium film and a titanium nitride film in this order from a lower layer, thereby forming a barrier metal film 107 comprising a laminated film of these two films. Afterwards, a tungsten film 108 is formed by a CVD method using tungsten fluoride (WF6) and an upper wiring formed of the barrier metal layer 107 and the tungsten film 108 is patterned on the interlayer insulating film 105.
FIGS. 8A to 8D are a schematic cross-sectional view showing a method of manufacturing another conventional semiconductor device. The semiconductor device is one in which a DRAM and a logic circuit are combined on the same substrate.
A DRAM-logic combined device is normally configured such that a silicide film is formed on an active region in a logic area to achieve high performance of a transistor, and no silicide film is formed on the active region in a DRAM cell area to reduce a junction leak.
In a DRAM cell area as shown in FIG. 8, a silicon plug (pad electrode) formed of a polycrystalline silicon film is formed on a source/drain diffusion layer of a transistor when the transistor and a bit line are connected to each other, and the silicon plug and the bit line formed thereabove are connected to each other. The method of manufacturing the semiconductor device, which is shown in FIGS. 8A to 8D, will be explained below. Incidentally, a description about a process step for forming a gate oxide film and a gate electrode on an active region will be omitted even in FIGS. 8A to 8D.
As shown in FIG. 8A, element isolation regions 202 are first formed on a silicon semiconductor substrate 201 by the so-called shallow trench isolation method. Next, a conductive layer 203 composed of an impurity of conductivity type opposite to the silicon semiconductor substrate 201 is formed on the silicon semiconductor substrate 201. The conductive layer 203 serves as a source/drain diffusion layer. In a logic area 220, a general cobalt silicide film 204 is formed on the conductive layer 203 as a contact layer. Thereafter, an interlayer insulating film 205 is formed over the whole surface of the silicon semiconductor substrate 201. In a DRAM cell area 221, part of the interlayer insulating film 205 is selectively etched to form a contact hole 206.
Next, as shown in FIG. 8B, a polycrystalline silicon film containing an impurity of the same conductivity type as the conductive film 203 is formed on the silicon semiconductor substrate 201 by a CVD method. The polycrystalline silicon film is removed on the interlayer insulating film 205 by etchback or a CMP method, whereby a silicon plug (silicon pad) 207 is formed.
Next, as shown in FIG. 8C, an interlayer insulating film 208 is further formed on the interlayer insulating film 205 by the CVD method. Contact holes 209 and 210 are simultaneously formed on the logic area 220 and the DRAM cell area 221.
Next, as shown in FIG. 8D, deposition based on an inorganic CVD method using titanium tetrachloride is done under the condition of temperatures ranging from about 400° C. to about 600° C. to form a titanium film and a titanium nitride film on the silicon semiconductor substrate 201 in this order from a lower layer, thereby forming a barrier metal film 211 comprising a laminated film of these two films. Afterwards, a tungsten film 212 is formed by a CVD method using tungsten fluoride and an upper wiring formed of the barrier metal film 211 and the tungsten film 212 is patterned on the interlayer insulating film 208.
However, the above-described conventional semiconductor device has caused such problems as shown below. The semiconductor device shown in FIGS. 7A to 7C is accompanied by a problem that the cobalt silicide film 104 at the bottom of the contact hole 106 is etched by etching at the formation of the contact hole 106, so that the thickness of the cobalt silicide film 104 at the bottom of the contact hole 106 becomes thinner than a region other than it. Further, a problem arises in that when the amount of overetching at the formation of the contact hole 106 increases, the contact hole 106 extends through the cobalt silicide film 104 to reach the conductive layer 103 located therebelow.
Therefore, a problem arises in that a contact resistance between the upper wring formed of the barrier metal film 107 and the tungsten film 108, and the cobalt silicide film 104 placed therebelow increases, thus degrading an electric characteristic. On the other hand, another problem arises in that when the thickness of the cobalt silicide film 104 is made thick to prevent an increase in contact resistance, a junction leak is degraded.
In the semiconductor device shown in FIGS. 8A to 8D, a bit line electrically connected to the conductive layer 203 needs to have a contact resistance stable over both the silicide film 204 in the logic area 220 and the silicon plug 207 in the DRAM cell area 221. With high integration of a recent semiconductor device, however, an aspect ratio of a contact hole increases and a coverage property is poor upon deposition based on a sputtering method. Therefore, the stabilization of the contact resistance on the silicide film 204 in the deep contact hole 209 falls into difficulties.
On the other hand, in order to improve the coverage property of the barrier metal film 211, the barrier metal film 211 has been deposited by the inorganic CVD method using titanium tetrachloride under the condition of temperatures ranging from about 400° C. to about 600° C. as described above. This method is accompanied by a drawback that although a contact characteristic at the bottom of the deep contact hole 209 in the logic area 220 can be improved, the contact hole 210 on the silicon plug 207 will cause a new problem.
This problem results in a problem that when the barrier metal film 211 is deposited or grown by the inorganic CVD method using titanium tetrachloride under the condition of temperatures ranging from about 400° C. to about 600° C., the silicon pad 207 and the barrier metal film 211 react with each other simultaneously with the deposition of the barrier metal film 211 to thereby cause missing of polycrystalline silicon constituting the silicon plug 207 directly below the contact hole 210, whereby the contact hole 210 is rendered open. This phenomenon depends on the thickness of the barrier metal film 211. The more the barrier metal film 211 becomes thick, the more the problem arises pronouncedly.